In this role you will carry out constrained random functional coverage based verification using SystemVerilog and UVM, working from spec coverage-closed verified and debugged designs, developing environments and leveraging 3rd party VIP as appropriate. You will verify blocks or sub-systems or top level within large and very complex networking or GPU/AI SOCs in advanced technology nodes down to 3nm FinFET.
Requirements

Key Responsibilities:

• Prime the verification activities for a block or an entire chip.
  
• Develop verification environment architecture using UVM.
  
• Document test environment associations and write test cases.
  
• Employ constrained random verification approaches when possible.
  
• Support lab bring-up with direct test cases.
  
• Perform code and functional coverage.
  

Key Qualifications:

• 8+ years of experience in ASIC verification.
  
• Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
  
• Significant experience with OVM/UVM methodologies.
  
• Familiarity with constrained random verification techniques, assertions and functional coverage.
  
• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.
  
• Team player – excellent interpersonal and communication skills.