VeeRteq Solutions Inc.
Markham, ON
Job Title: Sr. SILICON DESIGN ENGINEER Work Location: Markham, ON L3T 7X6 Duration: 9 Months Work Type: Contract Job Type: Onsite JOB Description:
- The Display Controller team within the client Technologies Group (RTG) is looking for a highly experienced Design professional with strong industry experience to join the IP deployment support team. As one of the major IP blocks with client, the Display Controller IP is delivered into leading edge discrete GPU, APU and semi-custom SOC programs whose execution teams spans the globe. The Display IP is one of the foundational IP's within client and is incorporated in all client SOC's which feature direct connectivity to a display device through Display Port, HDMI or USB-C connectors.
- As a proven leader, the candidate would work closely with client both IP and SOC team architecture and design leads to ensure the unique requirements of the Display IP and IP/SOC delivery are met. Such solutions are expected to be sustainable across multiple business units and require close collaboration with key technical leads across the organization to ensure successful program execution.
- As a member of the IP team, the candidate would be responsible for setup and execution of IP level synthesis runs, debug and analysis of results on a weekly basis. This position would require the individual to draw upon proven industry design experiences to ensure successful program execution.
- Define synthesis recipe with block leads
- Analyze results and debug any failures with design leads
- Act as a liaison between IP and SOC design teams for synthesis and physical layout issues
- Signoff IP quality for delivery into SOC
- Work with Central Engineering teams on new flow adoption and execution
- Effectively communicate results with multi-disciplined teams
- Gather, attend and present into technical status meetings on a weekly basis
- Proven RTL design experience on large ASIC development projects
- Strong background working with industry standard synthesis tools, flows and back-end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
- Strong background in Verilog, System Verilog and/or scripting
- Strong analytical skills and attention to detail
- Excellent written and communication skills
- Experience with display/display related technologies is an asset
- Understanding of the IP integration and interactions within an SOC is an asset
- Must be a self-starter and able to independently drive tasks to completion
- Demonstrates the ability to debug issues and quickly identify viable solutions
- Team player with proven leadership skills
- Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering