Position Name - Sr. Engineer (ASIC STA & CAD)

Type of hiring - Fulltime

Location - Markham, ON or Vancouver, BC (Onsite)

Key responsibilities:

• Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.
• Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management.
• Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
• Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures.

Qualifications:

• 10+ Years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs.
• Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must.
• Implementation experience and knowledge handing multi-voltage design is expected. STE closure of low power and multi-power mode designs is an added advantage.
• Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required.
• Proficiency in scripting language, such as, TCL, Pert and/or Python.
• Experience developing scripts to automate design flow, analysis.
• Hands-on experience with Physical Design implementation is a plus.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams.

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