Job Title: ASIC Verification LeadJob ID: DR840345511Location: Ottawa, ON Overview:Headquartered in Ottawa, our client serves the electronic design community from Canada, specializing in ASIC and FPGA design and verification, and embedded software development services. They are currently searching globally for a number of key technical resources, including a highly experienced ASIC Verification Lead. They are looking for world-class engineers, and that means worldwide searching. If you are an exceptional verification lead with an interest in coming to Canada to work with us, we want to hear from you. In this role you will help build and lead a highly experienced team of verification professionals performing constrained random functional coverage-based verification using SystemVerilog and UVM, working from spec to coverage-closed verified and debugged designs, developing environments, and leveraging 3rd party VIP as appropriate. Your team will verify blocks or sub-systems or top level within large and very complex networking or GPU/AI SOCs in advanced technology nodes down to 3nm FinFET. You will collaborate with strong and very experienced design leads in world-class ASIC environments with many clients.What you will be doing:

• Help build and lead a team verifying blocks, sub-systems or entire chips.
• Support ASIC lead on project planning and management ASIC front-end developments.
• Develop test and coverage plans as well verification environment architectures to be developed using using System Verilog and UVM.
• Document test environment associations and write test cases.
• Employ constrained random verification approaches when possible.
• Support lab bring-up with direct test cases.
• Perform code and functional coverage.

What you must have:

• 12+ years of experience in ASIC verification.
• Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
• Proven experience with the duties and responsibilities listed above.
• Significant experience with OVM/UVM methodologies.
• Experience developing test plans and coverage plans from scratch
• Experience architecting and developing multiple SV/UVM verification environments, both from scratch and through re-use
• Significant expertise in constrained random verification techniques, assertions and functional coverage.
• Experience with SONET, OTN, Ethernet, PCIe, video processing, GPUs, or AI is a significant asset.
• Team player and leader – excellent interpersonal and communication skills

For more information about TEEMA and to consider other career opportunities, please visit our website at www.teemagroup.comBy applying to TEEMA on any job portal implies you are entering into a business relationship with us and therefore grants TEEMA consent to send you further job updates or industry and company-related information.