Position Name - Sr. Engineer (ASIC with UVM)

Type of hiring - Fulltime/Subcon

Location - Markham, ON or Vancouver, BC (Onsite)

Job Description:

We are seeking a skilled Verification Engineer with a strong background in SoC, IP, and subsystem verification. The ideal candidate will have hands-on experience with ASIC design verification, UVM methodologies, and testing complex digital systems. The Candidate who has the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.

Key Responsibilities:

• IOHUB Subsystem test plan creation, DRVR implementation and verification closure.
• Closely work with Design/Architecture team to develop new verification components in the Testbench.
• Developing test plans, implementing drivers, building and enhancing verification components, and supporting interoperability testing at the system level.
• Support SoC to complete IOHUB IPs interoperability testing with external IPs at system level.
• Attend conference call for status sync up with global team.

Qualifications:

• A BSEE with 5+ Years or MSEE with 3+ Years of relevant experience is required.
• Proficiency in VHDL, Verilog/System Verilog, and test scripting (e.g., Perl, Shell, Makefiles) is essential.
• Familiarity with industry standards like PCI-e or HT, as well as virtualization and fabric technologies, is highly desirable.
• The role requires close collaboration with global teams and strong communication skills.
• Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
• Knowledge of Fabric and Virtualization is an asset.