Myticas Consulting
Ottawa, ON
Posted yesterday
Job Details:
Full-time
Experienced
Job Description
- ASIC Design Verification (block, subsystem, and full SoC levels)
- Strong SystemVerilog + UVM/OVM (testbench architecture, sequences, coverage)
- Develop verification plans, test strategies, and coverage models from specs
- Constrained random verification, assertions, and functional coverage
- Debug complex issues using waveform analysis and root-cause methodologies
- Experience with large, complex SoCs (AI, GPU, HPC, networking)
- Integration and use of 3rd-party Verification IP (VIP)
- Perform code coverage and functional coverage closure
- Strong RTL understanding (Verilog/SystemVerilog) for design validation
- Experience with processor architectures (ARM, MIPS, RISC-V)
- Familiarity with AMBA protocols (AXI, AHB, APB) and SoC interfaces
- Exposure to high-speed interfaces (PCIe, Ethernet, DDR, USB, SPI, I2C)
- Scripting for automation (Python, Perl, Tcl, Bash)
- Experience supporting lab bring-up, silicon validation, and post-silicon debug
- Knowledge of ASIC flows/tools (lint, LEC, STA, synthesis, PnR awareness)
Share This Job:
Frequently Asked Questions
This position is based in Ottawa, ON.
This is a full-time position.
The role focuses on ASIC design verification at block, subsystem, and SoC levels using SystemVerilog and UVM/OVM, verification planning, coverage models, constrained random verification, and debugging with waveform analysis.
Experience with large, complex SoCs (AI, GPU, HPC, networking) and integration of 3rd-party Verification IP is required.
Familiarity with AMBA protocols (AXI, AHB, APB) and high-speed interfaces like PCIe, Ethernet, DDR, USB, SPI, and I2C is required.
Strong RTL knowledge (Verilog/SystemVerilog), processor architectures (ARM, MIPS, RISC-V), and scripting for automation (Python, Perl, Tcl, Bash) are emphasized.
